Test Planning for Core-based Integrated Circuits under Power Constraints

Test Planning for Core-based 3D Stacked ICs under Power Constraints

Test planning for core-based 3D stacked ICs under power constraint is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-sta...

Wafer-Level Testing and Test Planning for Integrated Circuits

WAFER-LEVEL TESTING AND TEST PLANNING FOR INTEGRATED CIRCUITS by Sudarshan Bahukudumbi Department of Electrical and Computer Engineering Duke University

Test Set Minimization for Sequential VLSI Circuits Under Power or Time Constraints

This paper deals with two problems arising during the testing of sequential VLSI circuits, namely the test sequence compaction problem and the power minimization problem. Here is presented a unified model for both problems and is developed a common algorithmic framework to solve either one of these two problems. In this framework a fast and efficient heuristic subsequence selection method is im...

Software-based self-test under memory, time and power constraints

Dynamically Partitioned Test Scheduling for SoCs Under Power Constraints

Test scheduling increases parallelism of test application and reduces the test cost. In this paper, we present a novel scheduling algorithm for testing embedded core-based System-on-Chips. Given a system integrated with a set of cores and a set of test resources, we construct a set of power constrained concurrent test sets from a power-constrained test compatibility graph (P-TCG). Furthermore, ...